1. Field
The embodiments discussed herein are each directed to an operational amplifier circuit. In recent years, in the field of semiconductor integrated circuit (IC) devices, technological development has rapidly progressed to achieve further reduction in power consumption and power supply voltage. For an operational amplifier circuit onto a semiconductor IC device, it is necessary that an allowable range of an input signal voltage is expanded to a power supply voltage range, and stabilized operation is secured.
2. Description of the Related Art
FIG. 1 illustrates a conventional operational amplifier circuit. The operational amplifier circuit has a configuration including first and second differential amplifier circuits, 1a and 1b, which respectively receive input signals IN1 and IN2, a level shifter unit 2, which receives output signals of the respective differential amplifier circuits 1a and 1b, and an output circuit 3 to be driven by the level shifter unit 2.
The first and second differential amplifier circuits 1a and 1b are provided in order to output an output signal OUT at a full amplitude from the output circuit 3 even in the event the respective input signals IN1 and IN2 approach either the level of a high electrical potential power supply Vcc or low electrical potential power supply Vss (the “electrical potential” hereinbelow will be simply referred to as “potential”).
More specifically, when the input signals IN1 and IN2 approach the level of the power supply Vcc, the second differential amplifier circuit 1b does not substantially operate while the first differential amplifier circuit 1a operates and outputs an output signal of its own to the level shifter unit 2.
Alternatively, when the input signals IN1 and IN2 approach the level of the power supply Vss, the first differential amplifier circuit 1a does not substantially operate while the second differential amplifier circuit 1b operates and outputs an output signal of its own to the level shifter unit 2.
Still alternatively, when the input signals IN1 and IN2 are each at an intermediate level between the power supplies Vcc and Vss, the first and second differential amplifier circuits 1a and 1b both operate.
In the level shifter unit 2, nodes N1 and N2, having level shifted the output signals of the first and second differential amplifier circuits 1a and 1b, are connected to gates of a pull-up transistor T1 and a pull-down transistor T2 of the output circuit 3. The level shifter unit 2 generates a certain level shifted voltage ΔV between the nodes N1 and N2.
The level shifted voltage ΔV preferably satisfies expression (1) below:ΔV=Vcc−(Vgsp1+Vgsn2)  (1)Where Vgsp1 is a gate-source voltage of the transistor T1 of the level shifter unit 2, when the output current of the output circuit 3 is an ideal value 12; and Vgsp2 is a gate-source voltage of the transistor T2 of the level shifter unit 2, when the output current of the output circuit 3 is an ideal value 12.
More specifically, a current I1 is represented by expression (2) below:I1=(Vcc−Vgsn3)/R1  (2)where Vgsn is a gate-source voltage of a transistor T3 of the level shifter unit 2.
The level shifted voltage ΔV is represented as expression (3) below:ΔV=R2/R1×(Vcc−Vgsn3)  (3)
Accordingly, it is preferable that expression (4) below is satisfied:Vcc−(Vgsp1+Vgsn2)=R2/R1×(Vcc−Vgsn3)  (4)where R1 and R2 are resistors of the level shifter unit 2.
For example, a relational expression of the above takes the form of expression (5) shown below when, for example, Vcc =3V, Vgsp1=0.5V; and Vgsn2, Vgsn3=0.5V.Vcc−(Vgsp1+Vgsn2)=R2/R1×(Vcc−Vgsn3)3.0V−(0.5V+0.5V)=R2/R1×(3.0V−0.5V)R2/R1=4/5  (5)
The above is indicative that an ideal operation can be achieved when the design is carried out so that the ratio between the resistance values of resistors R1 and R2 of the level shifter unit 2 is 5:4.
In addition, supposing that, given the ratio 5:4 between the resistance values of the resistors R1 and R2, the state is changed in accordance with transistor threshold values changed due to process variations, such as: Vgsp1=0.8V; and Vgsn2, Vgsn3=0.8V. In this case, the relational expression takes the form of expression (6) given below.Vcc−(Vgsp1+Vgsn2)=3.0V−(0.8V+0.8V)=1.4 VR2/R1×(Vcc−Vgsn3)=4/5×(3.0V−0.8V)=1.76VVcc−(Vgsp1+Vgsn2)≠R2/R1×(Vcc−Vgsn3)  (6)
Consequently, the level shifted voltage ΔV is offset from the ideal value due to an offset in the transistor threshold value, thereby leading to, for example, an increase in offset voltage error and/or an offset in the ideal value I2.
Thus, according to the operational amplifier circuit of FIG. 1, the level shifted voltage ΔV can be preliminarily set to the ideal value by setting the resistance values of the resistors R1 and R2. When the transistor threshold value is offset due to process variations, however, the level shifted voltage ΔV is offset from the set value.
Thus, one drawback of operational amplifier circuit is that, in the state where the power supply voltage is low, the offset in the level shifted voltage ΔV associated with the offset in the transistor threshold value, poses the problem of significantly reducing the accuracy of the output signal of the operational amplifier circuit.
Japanese Laid-Open Publication No. 2002-43871 discloses an operational amplifier circuit, in which the sum of current values of bias currents for supply to first and second input differential pair is controlled to be constant, thereby suppressing fluctuations in characteristics due to process variations.
Japanese Laid-Open Publication No. 2001-60832 discloses a configuration for reducing power consumption in the preceding circuit for driving respective transistors of a complementarily connected output circuit.
Japanese Laid-Open Publication No. 06-85570 discloses an operational amplifier circuit apparatus including a P-top operational amplifier circuit and an N-top operational amplifier circuit, in which any one of the operational amplifier circuits is operated in accordance with the voltage level of an input signal.
Other objects, features, and advantages will be apparent to persons of ordinary skill in the art from the following description of the invention and the accompanying drawings.